1. Field of the Invention
The invention relates to insulation structures, and particularly to improving the characteristics of trench isolation structures in which polysilicon is used as a trench fill material.
2. Description of the Related Art
A typical integrated circuit, manufactured on a silicon substrate, comprises a series of active devices formed in and on the silicon substrate. Each active device is formed by introducing impurities into a surface of the substrate, generally through the use of implantation or diffusion of the impurity, to vary the conductivity of different regions of the substrate. This requires a series of processing steps which include masking selected portions of the wafer to place the impurities at selected locations on the wafer. A substrate will generally have a first conductivity type, with the impurities selected to form regions in the substrate of opposite conductivity type or to enhance conductivity of the substrate. The active devices are electrically isolated from other active devices through the use of various electrical isolation schemes.
In forming some types of integrated circuits, particularly bipolar devices, it is desirable to provide layers of impurity which are "buried" below the surface of the substrate. Traditionally, a buried layer was formed in a substrate prior to the deposition of epitaxial silicon on the surface of a single crystal substrate, with the active devices subsequently formed in the polysilicon.
While several processing techniques are conventionally available to achieve such buried regions, advances in wafer processing technology have increased the popularity of so-called "bonded" wafers.
In bonded wafer technology, two single-crystal substrates are joined so that impurities can be introduced into a first surface of a first wafer to form an impurity region which subsequently becomes a buried region when the first wafer is bonded to a second or "handle" wafer at the first surface. In general, the handle wafer is comprised of a semiconductor having a first conductivity type, such as a p-type impurity, while the first substrate is comprised of a second conductivity type, such as an n-type impurity.
The handle wafer is "bonded" to the first substrate through any number of techniques. Bonding may occur through Van der Waals forces (where polishing tolerances are exacting, as disclosed in U.S. Pat. No. 4,638,552) or through the use of a thin oxide layer between the surfaces (such as in U.S. Pat. No. 4,968,628). After formation of the oxide, the substrates are heated to ensure bonding of the substrates to each other. This latter process is illustrated in FIGS. 1-4.
FIGS. 1-4 are cross sections generally showing the procedure for manufacturing an active device having a buried layer using a bonded wafer technique and junction isolation. Each of the active devices in an integrated circuit must be electrically isolated from the adjoining active region to prevent cross-over electrical effects between adjoining devices which would defeat overall operation of the circuit. The devices are thereafter connected to a series of metal or metal-alloy interconnect structures to complete the integrated circuit device.
FIG. 1 shows a p-type silicon substrate 10. Substrate 10 will have formed therein, for example, a p+ type region 12 by implantation or diffusion. Region 12 will become a buried layer formed in substrate 10 by selected diffusion. The surface of substrate 10 must be polished to a high tolerance surface thickness, such as by chemical mechanical polishing, and may have a thin oxide layer formed thereon such as shown in FIG. 2. Oxide layer 14 is formed on the surface of substrate 10.
As shown in FIG. 3, a handle wafer 15 is thereafter bonded to substrate 10. Handle wafer 15 is generally an n-type substrate and will also have a thin layer of oxide formed on the surface to be bonded, such surface also being polished to a high degree of smoothness. The oxide on the handle wafer will contact oxide layer 14 on the surface of substrate 10. The wafers may then be heated to a temperature of about 1,000.degree. C. and held there for a period of time of about one hour. This causes the oxide layers to bond, thereby joining wafers 10 and 15. The resulting combined oxide layers 14' define the desired dielectric isolation thickness. Further processing can then occur on the backside 16 of substrate 10. Note that n+ region 12 becomes a buried region within the completed assembly.
As shown in FIG. 4, an n well 19 will be formed in substrate 10, and p+ emitter and collector contacts 17,18, and n+ base contact 20 may be formed to complete a bipolar transistor.
While additional n+ regions 11 may be provided to serve as reverse biased PN junction lateral device isolation, the degree of isolation afforded by junction isolation is limited by collector-substrate leakage currents and collector-substrate capacitance. Several alternative isolation techniques have developed to prevent leakage currents from impeding device performance, including dielectric isolation and trench isolation. Dielectric isolation typically comprises etching pockets in a wafer surface, oxidizing the pockets, and backfilling the pockets with polysilicon. The wafer may then be turned over, ground and polished until the original oxide layer is reached, leaving oxide isolated pockets of the original silicon material in which active devices may be formed.
Trench isolation involves etching a trench into the substrate, and filling the trench with an insulation material. Trench isolation is relatively complex because an anisotropic etch must be used to define the trench, the trench must be etched deeply into the silicon, and filling the trench with the isolation material can give rise to additional processing issues in preparing the integrated circuit. After the trench is formed in the substrate wafer, a layer of insulating material such as silicon dioxide is deposited over the surface of the wafer into the trench by a conformal deposition process, such as TEOS oxide. While silicon dioxide can fill the trench completely, this creates a great deal of stress in the substrate. Thus, the conformal layer of TEOS oxide will generally be deposited in a quantity sufficient to provide the requisite isolation, but not completely fill the trench. The remaining portion of the trench will be filled with polysilicon which has nearly identical characteristics to bulk silicon, thus reducing stress in the substrate.
This process is illustrated in FIGS. 5-7. FIG. 5 shows a cross section of a bonded wafer structure. As shown in FIG. 5, a trench 29 is anisotropically etched into the substrate 10. The etch is made using a directional etch process, such as planar plasma etching, ion beam etching or reactive ion etching, with an oxide mask layer (not shown) which is patterned to expose the trench region to be etched. The silicon substrate 10 in the trench region is etched down to oxide layer 14'. Thereafter, a TEOS oxide 34 is deposited on the second surface 13.sub.2 of substrate 10. As shown in FIG. 6, the TEOS oxide 34 covers surface 13 and the sidewalls 21, 22 of trench 29. The TEOS oxide is a conformal deposition process and results in a relatively uniform oxide thickness in the range of 2-4 K .ANG. on the bottom and sidewalls of trench 29. The remaining volume of trench 29 is filled with polysilicon 35 and the portion of oxide 34 on the surface 13.sub.2 of substrate 10 is thereafter removed. As shown in FIG. 7, polysilicon 35 is thus electrically isolated from the remaining portions of silicon substrate 10.
Oxide layer 34 will be deposited to a thickness which is sufficient to provide the requisite isolation which is required based upon the particular active devices being formed. Polysilicon 35 is deposited in a trench as the preferred means of filling the remaining void, since polysilicon is thermally matched to the silicon comprising substrate 10. Thus, less stress will occur in the wafer with polysilicon in the trench during subsequent processing than were oxide used as the sole trench fill material. As a result of its electrical isolation, polysilicon 35 can act as a charge capacitor and, in certain circumstances, an inversion region 41 is induced in the silicon adjacent to oxide 34 and between two separate p+ diffused regions 27,28, as shown in FIG. 8. Diffused p+ regions 27,28 may comprise, for example, the emitter and collector of a PNP bipolar transistor. The inversion region 41 in the device silicon forms a conductive path between regions 27,28, essentially shorting the circuit.
Thus, the integrity of the active device in a given active region can be compromised.
One method previously used to cure this problem was to provide polysilicon "tabs" which allow coupling of the polysilicon to a charge dissipation mechanism. Provision of such tabs requires a separate masking and polysilicon deposition step to ensure the contacts are large enough to enclose a normal-sized contact.